Semiconductor diodes, in particular gated-diodes, are often used in CMOS integrated circuits for important analog circuit functions including temperature sensing and bandgap reference voltage applications. For the analog applications to properly function, the forward-bias diode characteristics should be nearly ideal, as measured by the diode ideality factor (n) which should be nearly equal to a value of 1. In advanced CMOS technologies, achieving a gated-diode structure with good ideality near 1 can be challenging because of the widespread use of Reactive Ion Etching (RIE), which can damage then semiconductor structures. RIE related damage is known to degrade diode ideality. Thus, in order to achieve a good diode ideality, the RIE damage should be eliminated or minimized.
Diodes in general are formed by creating abutting semiconducting regions of N-doped (excess electrons) and P-doped (excess holes). Preferably, one but not both regions is more heavily doped, creating either an N+/P diode or a P+/N diode. N-doped regions are typically formed by implanting or diffusing N-type donor dopant species, such as arsenic or phosphorus, into the semiconductor material such as silicon. Similarly, P-doped regions are formed by implanting or diffusing P-type acceptor dopant species, e.g., boron into a region adjacent to and contacting the N-type region. Typically, a dopant activation thermal cycle or heating is necessary to make the dopants electrically active.
Gated-diodes formed as described, with the addition of a gate electrode and gate dielectric located at or near the location of the P-N junction. Often but not always, the gate electrode serves as a masking structure to allow creating a self-aligned P-N diode wherein the edge of the gate electrode defines the location of the P-N junction. Self-alignment can be achieved when the P-N junction is formed by ion implantation, and the gate electrode is sufficiently thick to block either the heavier P+ or N+ region implant from penetrating through to the underlying semiconductor substrate, and is wide enough laterally to allow a photolithography mask to consistently land on the gate even in the presence of loose manufacturing alignment tolerances. Generally, it can be advantageous to achieve good diode ideality by locating the P-N junction underneath the gate electrode and gate dielectric because this region is typically a high quality interface largely free of defects. Avoiding defects in and around the P-N junction region is important for achieving good ideality, as defects are known to create generation and/or recombination sites which degrade the diode ideality.
Dielectric capping layers (such as nitride or oxide) on top of gates are commonly used in CMOS fabrication. Examples of the uses for these dielectric capping layers include use as a hard mask for gate electrode patterning and increasing the gate stack thickness for ion implantation blocking effectiveness. A gate electrode hard mask is a layer or layers patterned on top of a blanket gate electrode, which protects desired regions from RIE, thus forming patterned gate electrodes. This is in contrast to soft mask based patterning where the pattern is formed using photoresist. Oftentimes it is beneficial to keep the dielectric hard mask on top of the gate even after the gate electrode etching has been completed and during subsequent ion implantation steps required for building the gated-diode and Field Effect Transistors (FET). The additional dielectric layer contributes to blocking ion implantations, such as source/drain or halo implants from penetrating through the gate electrode into the channel. The dielectric layer is typically removed by RIE prior to a silicide formation, to enable the gate electrode region to be silicided. However, RIE can damage and introducing defects within and nearby the gated diode (P-N junction) region, resulting in a degraded ideality, that ultimately leads to poor circuit functionality in temperature sensor, bandgap reference voltage and other analog circuits that rely on good diode ideality.
Generally, all the gates and diffusions of a sub 250 nm technology have silicide formed to minimize resistance, knowing that silicidation of silicon and polysilicon regions reduces the resistance which results in increased transistor and circuit performance.
FIG. 1 is a perspective view of a prior art structure for a diode and a FET as part of integrated circuit. For simplicity, a single N-FET is shown, but it should be understood that N-FETs and P-FETs can be used together as part of CMOS integrated circuits. The fabrication sequence for the conventional structure shown in FIG. 1 results in damage to the diode which degrades the diode ideality. Note that in this prior art structure and P+/N diode is shown, but it should be understood that an N+/P diode can also be used.
Accordingly, there is a need for a structure that provides the benefits of a dielectric capping layer on top of the gate electrode of the gated-diode to avoid the diode ideality degradation of removing the capping layer that is desired for advanced CMOS integrated circuits.